:? Horizontal sync input may be up to 120 KHz.
? On-chip PLL circuitry up to 96 MHz.
? Programmable horizontal resolutions up to 1524 dots per display
row.
? 942 bytes display registers to control full screen display.
? Full screen display consists of 15 (rows) by 30 (columns) characters.
? 12 x 18 dot matrix per character.
? Total 256 characters and graphic fonts including 248 mask
ROM fonts and 8 programmable RAM fonts.
? 8 color selectable maximum per display character.
? Double character height and/or width control.
? Programmable positioning for display screen center.
? Bordering, shadowing and blinking effect.
? Programmable vertical character height (18 to 71 lines) control.
? Row to row spacing register to manipulate the constant display
height.
? 4 programmable background windows with multi-level operation
? Software clears for display frame.
? Polarity selectable to Hsync and Vsync inputs.
? Auto detection for input edge bounce distortion between Hsync
and Vsync inputs.
? Half tone and fast blanking output.
? Software force blank function for external display.
? 8 channels 8 bits PWM D/A converters output.
? Provide a clock output synchronous to the incoming Hsync for
external PWM D/A.
? Compatible to SPI bus or I2C interface.
? I2C interface with address 7AH (Slave address is mask option).
? 16 pins or 24 pins PDIP package.